CMP=0, USBOTG=0, I2C1=0, CMT=0, UART1=0, EWM=0, VREF=0, I2C0=0, UART0=0, UART2=0, UART3=0
System Clock Gating Control Register 4
| EWM | EWM Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| CMT | CMT Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| I2C0 | I2C0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| I2C1 | I2C1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART0 | UART0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART1 | UART1 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART2 | UART2 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| UART3 | UART3 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| USBOTG | USB Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| CMP | Comparator Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
| VREF | VREF Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |